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Frequently Asked Questions

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Why does a differential signal travel faster than a common signal on a microstrip? The primary quality that determines the speed of the differential or common signal is the effective dielectric constant the signal sees.  In a tightly coupled differential microstrip, the differential signal propagates in the odd mode with electric fields that extend into the air above the signal lines. The field lines see an effective dielectric constant that is significantly lower than the bulk value due to the contribution of all that air. This lower effective dielectric constant means a faster speed and a shorter time delay. A common signal on the other hand, propagating in the even mode of the microstrip, has very little field contribution in the air above the trace. Most of the electric field is in the bulk material under the signal lines. This means the effective dielectric constant the common signal sees is closer to the bulk value. A higher effective dielectric constant means a slower speed and a longer time delay. If the lines in the differential pair are very weakly coupled, then there is no difference in the field distributions between the odd or even modes and there is no difference in the effective dielectric constant the differential or common signals see. Thus, there is no difference in the speed of a differential and common signal in microstrip that are not coupled, or in stripline. For more information come to the Essential Principles class. What is the single most critical improvement that needs to be made on the board (PCB) to reach >10Gbs data rates (DK, DF, T-Line routing)? There is one critical improvement in a board that must be made and one improvement in the transceivers that drive a high speed signal. All resonances from stubs, of any sort, must be kept short enough so that their resonance frequency is above about 5 x the Nyquist frequency, or above about 25 GHz, for 10 Gbps signals. The resonance frequency of a stub is 1500 GHz/length (in mils). For the resonant frequency to be above 25 GHz, requires the stub length to be shorter than 60 mils. In addition to using strictly a point to point routing architecture, it is important to use vias with residual stubs shorter than 60 mils. This can be achieved by backdrilling or using blind or buried vias. This is the one most important feature of a board to achieve 10 GHz operation. FR4 has another limitation related to its losses. If the transceivers have pre-emphasis and equalization, they can overcome as much as -30 dB of dielectric and conductor losses. This combination can enable conventional FR4 to be used above 10 Gbps. If this is important for your application, you should take the Best Board Design Principles class. You mention that, “Many boards are over-designed with too many capacitors”. What does that mean? Designing the power distribution network efficiently is hard. There are a number of unknowns that you need which are hard to get. For example, what is the peak current draw of the chip? At what frequency does this occur? How much on-chip decoupling capacitance is there? What is the effective package loop inductance? We often have to make decisions NOW! Without all the information we need. the way we minimize the risk in such situations is by adding design margin. We can make some guesses about the impedance requirements and the on-chip capacitance. For example, if we assume a max current of ¼ Amp per power/gnd pin pair, and an ESL of 2 nH for the decoupling capacitors, then, one way of providing a low enough impedance profile across the frequency range from 1 MHz to 100 MHz, is with 8 capacitors, two each of 1 uF, 0.1 uF, 0.01 uF and 0.001 uF. If you aren’t going to do any circuit simulations, this will get you a robust decoupling profile. If there are 8 power and ground pin pairs, this approach would require 64 capacitors. However, if you are willing to sculpt the profile with a SPICE simulation, then using only 20 capacitors, with the right values, you can obtain a comparable impedance profile. This is 1/3 the number of capacitors from the simple rule of thumb. If you want to use really low L capacitors like X2Y capacitors, you can further reduce this to less than 10 capacitors. In general, most designers do not use analysis in their design of the PDN. It doesn’t mean their designs won’t work. However, if it does work, it is probably not optimally designed and has many more capacitors than might be needed. The only way to know for sure is by running a simulation. Examples of these simulations are illustrated in online lecture OLL-803. Why are all busses moving toward point to point routing architectures and not just higher speed multi-drop busses? All end user applications will always demand higher and higher data rates, between chips, between boards and between cabinets. As data bandwidths have increased above the Gigabits/sec per channel rate, signal integrity limitations from the interconnects have forced a revolutionary change in transmission architectures. Reflection noise from stubs in parallel, multi-drop busses due to packages, termination resistors and routing constraints, limit the shortest rise times before noise is excessive to about 0.3 nsec rise times. CMOS technology has advanced into the regime where interconnects can’t keep up with the possible data rates using a parallel topology. When CMOS is capable of delivering higher data rates than the interconnect architecture can support, something has to change. Enter serial networks, where the interconnect topology is point to point. In this environment, signal integrity can be much more tightly controlled, opening up pathways with possible bandwidth limits well above 10 Gbps. In serial networks, all interconnects are point to point differential channels, but the maximum data rates are still often set by the combined effects of inteconnect losses, impedance discontinuities, cross talk and intra-line skew. This is why it is so important to evaluate each new interconnect structure to determine its suitability for a high speed serial standard. Question from Jim Nodolny of Samtec: I'm designing a high speed digital connector and to meet some mechanical requirements I am looking at a pin made of an iron alloy with gold plating.  The gold plating will get me the required contact physics properties for durability, contact resistance, etc.  but I got to thinking about the iron alloy base material. What impact will the high permeablity have on signal integrity? The internal self inductance of the lead will increase, due to the high permeability of the iron, which in turn will increase the loop inductance. But it turns out to not be much of an issue above 1 MHz. There is another problem to watch out for, though. The skin depth scales inversely with the sqrt of the permeability. A high permeability means a thinner skin depth at lower frequency than in copper. This means at about 1 MHz, the current is mostly on the outer surface and there are no internal magnetic field lines in the high permeability material, so no impact on the loop inductance. I gave a presentation about 15 years ago on the loop inductance of alloy 42 lead frames vs copper lead frames and showed at 100 kHz, the loop inductance of the alloy 42 (high permeability) was about 5x that of the copper lead frame, but by 10 MHz, the loop inductance of the alloy 42 had dropped to the same as the copper lead frame. However, the problem with the high permeability material is the skin depth is so small. This means the series resistance of your lead can potentially by much higher than an equivalent copper lead, by 10-100x. The plating will help to buffer this problem, which is what self equalizing cables do, as you point out. The trick that used to be used on alloy 42 lead frames was to over plate the lead frame with 80 microinches of silver. This provided a wire bondable surface on one end, a solderable surface on the other and gave good DC and low frequency resistance. You'll want to put in the numbers to see what thickness plating you need to achieve your low frequency resistance specs. Of course, if it's short enough, it may not matter. Submitted by Dance Wu, Marvell: I have heard that Microstrip radiates about 25 times more over stripline structure, Why is this? First, the radiation from Microstrip is really, really small. There are no good approximations for it, other than the magnetic dipole antenna model, and this is for a narrow wire, not a trace over a wide ground plane. So, the fact that there may be a 25 dB difference between microstrip and stripline, doesn’t mean avoid microstrip because it radiates. The largest source of radiation in microstrip is from the finite width plane. It is the inductance in the return path that causes a very small ground bounce across the plane which actually does the radiating. The reason stripline radiates much less is related to the distribution of the currents. The easiest way of thinking about it is to first consider a coax. There are no external fields around a coax because the return current is symmetric in the shield with the signal current in the central conductor. Since there are no E or B fields external to the conductor, there is no ground bounce in the cable nor any radiation. The more you can make a signal topology look like a coax, the less it will radiate. In stripline, the return currents are mostly symmetrical on either side of the signal current and there is little B field around the combination of signal and return path. If the signal line is more than 5 x h from the edge, where h is the total separation between the planes, then there is virtually no external E or B field and very little radiation. In general, it is almost always ground bounce in the planes- voltage drops from one region to another, that turn the planes into patch antennas that ultimately results in EMI- its not the signal traces themselves that do the radiating. Of course, a far bigger source of EMI is common currents in external cables, but the direct radiated emissions from boards usually comes from the planes, not the signal traces